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[\/et_pb_text][\/et_pb_column][\/et_pb_row][\/et_pb_section][et_pb_section fb_built=”1″ custom_padding_last_edited=”on|desktop” disabled_on=”on|on|on” admin_label=”section” module_class=”blurb-list background-4″ _builder_version=”4.17.4″ custom_padding=”||100px|” custom_padding_tablet=”50px|0|50px|0″ custom_padding_phone=”” da_disable_devices=”off|off|off” border_color_bottom=”#5c94d4″ disabled=”on” collapsed=”on” global_colors_info=”{}” da_is_popup=”off” da_exit_intent=”off” da_has_close=”on” da_alt_close=”off” da_dark_close=”off” da_not_modal=”on” da_is_singular=”off” da_with_loader=”off” da_has_shadow=”on”][et_pb_row _builder_version=”4.16″ global_colors_info=”{}”][et_pb_column type=”4_4″ _builder_version=”4.16″ custom_padding=”|||” global_colors_info=”{}” custom_padding__hover=”|||”][et_pb_text admin_label=”H2: Recent publications” _builder_version=”4.16″ text_text_color=”#e02b20″ header_text_color=”#e02b20″ global_colors_info=”{}”]<\/p>\n
Recent publications<\/h2>\n
[\/et_pb_text][\/et_pb_column][\/et_pb_row][et_pb_row column_structure=”1_2,1_2″ _builder_version=”4.16″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” global_colors_info=”{}”][et_pb_column type=”1_2″ _builder_version=”4.16″ custom_padding=”|||” global_colors_info=”{}” custom_padding__hover=”|||”][et_pb_blurb title=”InPulse 3 – A New Horizontal Cu Plating System for mSAP\/amSAP Technology” url=”https:\/\/www.atotech.com\/wp-content\/uploads\/2020\/03\/EIPC-winter-conference_InPulse-3-New-Hor-Cu-Plating-System-for-mSAP-am….pdf” url_new_window=”on” use_icon=”on” font_icon=”h||divi||400″ icon_color=”#5992d6″ icon_placement=”left” admin_label=”InPulse 3 – A New Horizontal Cu Plating System for mSAP\/amSAP Technology” _builder_version=”4.16″ header_text_color=”#5992d6″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” max_width_tablet=”50px” z_index_tablet=”500″ global_colors_info=”{}”]<\/p>\n
This paper describes a new horizontal copper plating process especially designed to transport very thin panels with a thickness down to 30 \u03bcm (25 \u03bcm Substrate with 2\u00d72 \u03bcm copper clad). It also shows first plating results with the combination of this new equipment together with the new developed dedicated electrolyte. The new system is designed enable pattern plating and the use of (a)mSAP processes towards lines\/ spaces in the range of 20\/20 \u00b5m. The paper was first published during EIPC winter conference in February 2020.<\/p>\n
2020, PDF, 1,119 KB<\/p>\n
[\/et_pb_blurb][\/et_pb_column][et_pb_column type=”1_2″ _builder_version=”4.16″ custom_padding=”|||” global_colors_info=”{}” custom_padding__hover=”|||”][et_pb_blurb title=”Filling of Microvias and Through Holes by Electrolytic Copper Plating \u2013 Current Status and Future Outlook” url=”\/wp-content\/uploads\/2019\/03\/IPC_APEX_2019_Filling-of-BMVs-and-THs-by-Electrolytic-Copper-Plating.pdf” url_new_window=”on” use_icon=”on” font_icon=”h||divi||400″ icon_color=”#5992d6″ icon_placement=”left” admin_label=”Filling of Microvias and Through Holes by Electrolytic Copper Plating \u2013 Current Status and Future Outlook” _builder_version=”4.16″ header_text_color=”#5992d6″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” max_width_tablet=”50px” global_colors_info=”{}”]<\/p>\n
\nThis article was created in cooperation with GreenSource Fabrication LLC., USA and was originally presented on IPC APEX EXPO 2019. The paper describes the reasons for development of copper via filling and a roadmap of dimensions for copper filled through holes, microvias and showing aspects of other copper plated structures on PCBs. Furthermore, it contains feasibility studies of new electroplated structures for future applications such as copper pillar plating on IC-substrates.<\/p>\n
2019, PDF, 540 KB<\/p>\n
[\/et_pb_blurb][\/et_pb_column][\/et_pb_row][et_pb_row column_structure=”1_2,1_2″ _builder_version=”4.16″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” global_colors_info=”{}”][et_pb_column type=”1_2″ _builder_version=”4.16″ custom_padding=”|||” global_colors_info=”{}” custom_padding__hover=”|||”][et_pb_blurb title=”Enhancing Productivity for IC-substrate manufacturing by using a novel Copper Electrolyte for Semi Additive Plating” url=”\/wp-content\/uploads\/2019\/03\/2018-10_EPTC-Sigapore_novel-Copper-Electrolyte-for-SAP.pdf” url_new_window=”on” use_icon=”on” font_icon=”h||divi||400″ icon_color=”#5992d6″ icon_placement=”left” admin_label=”Enhancing Productivity for IC-substrate manufacturing by using a novel Copper Electrolyte for Semi Additive Plating” _builder_version=”4.16″ header_text_color=”#5992d6″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” max_width_tablet=”50px” z_index_tablet=”500″ global_colors_info=”{}”]<\/p>\n
\nThe Semi Additive Process (SAP) has gained more attraction over the past years because it enables very fine lines and spaces for the production of IC-substrates. When operating with lines and spaces (L\/S) of 10\/10 \u03bcm and less, the copper thickness variation is one of the critical parameters which has to be controlled within a tight range in order to avoid reliability problems in assembly or during the lifetime. This paper contains the results of our investigations on our latest via filling process for IC-substrates with regards to copper thickness variation (WUD), dimple results, filling performance and microsection pictures.
This article was originally published on EPTC 2018, Singapore.<\/p>\n
2018, PDF, 320 KB<\/p>\n
[\/et_pb_blurb][\/et_pb_column][et_pb_column type=”1_2″ _builder_version=”4.16″ custom_padding=”|||” global_colors_info=”{}” custom_padding__hover=”|||”][et_pb_blurb title=”Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost” url=”\/wp-content\/uploads\/2019\/03\/2018-09-14_IMAPS2018_Upscaling-panel-size-for-Cu-plating-on-FOPLP-applications-to-reduce-manufacturing_rev.pdf” url_new_window=”on” use_icon=”on” font_icon=”h||divi||400″ icon_color=”#ffffff” icon_placement=”left” admin_label=”Upscaling panel size for Cu plating on FOPLP (Fan Out Panel Level Packaging) applications to reduce manufacturing cost” _builder_version=”4.16″ header_text_color=”#5992d6″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” max_width_tablet=”50px” z_index_tablet=”500″ global_colors_info=”{}”]<\/p>\n
The ever increasing demand of higher performance, lower cost and thinner end user devices like smartphones require intense developments and innovation in all areas of the electronic component design including the substrate and chip packaging. Latest manufacturing technologies in both areas like fan-out wafer level packaging and advanced substrates are constantly emerging and promise to be a critical piece to meet these requirements. The paper presents latest studies and conclusions in critical performance areas of the plating process such as electrolyte fluid dynamics, impact of anode design, pulse reverse rectification and newly designed electrolytes on panel sizes of up to 600 mm.
This article was originally published on IMAPS 2018, Pasadena.<\/p>\n
2018, PDF, 900 KB<\/p>\n
[\/et_pb_blurb][et_pb_blurb title=”Fine line through hole copper filling in VCP for next generation packaging” url=”\/wp-content\/uploads\/2019\/03\/2017_SMTA_Fine-line-TH-copper-filling-in-VCP-for-next-gen.-packaging.pdf” url_new_window=”on” use_icon=”on” font_icon=”h||divi||400″ icon_color=”#5992d6″ icon_placement=”left” disabled_on=”on|on|on” admin_label=”Fine line through hole copper filling in VCP for next generation packaging” _builder_version=”4.16″ header_text_color=”#5992d6″ background_size=”initial” background_position=”top_left” background_repeat=”repeat” max_width_tablet=”50px” z_index_tablet=”500″ disabled=”on” global_colors_info=”{}”]<\/p>\n
\nThis paper presents the complete through hole filling for cores using a Cu electroplating process for IC Package production, especially for FC-BGA and FC-CSP. In detail the influence of electrolyte agitation, current density, inorganic and organic concentrations on the filling performance are described and discussed. The result of our investigations is a process with improved TH filling capability at low void occurrence and excellent within-unit distribution.
The article was originally published on SMTA 2017, Chicago.<\/p>\n
2017, PDF, 510 KB<\/p>\n
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